Augmented Virtual Impedance-Based Fault Ride Through of Islanded Microgrids Under Harmonic and Unbalanced Conditions

Abstract

Reducing the control effort and limiting the output current of grid-forming inverters with the ability of voltage distortion prevenience in islanded microgrids under harmonic and asymmetrical fault conditions are the main objectives of this paper, which have not been investigated so far. In the proposed fault ride through (FRT) approach for inverter-based distributed generation (DG) resource, the current limiting strategy (CLS) only decreases the fundamental component of the reference value of inverter current to a value less than the threshold limit. In other words, harmonic components of the reference value of the inverter current remain unchanged in the proposed CLS to prevent DG’s output voltage distortion. Moreover, an adaptive reference voltage modification scheme is designed based on the virtual impedance concept and by using the reference current reduction coefficient obtained from the proposed CLS. This scheme avoids the voltage controller saturation as well as eliminates the need to use the anti-windup technique for the proportional-resonant (PR) controller. The output impedance-based stability analysis is also performed based on the closed-loop dynamics of the proposed FRT approach to present a basis for the selection of the key parameter. Comparative studies performed by MATLAB/SIMULINK software approve the superior performance of the proposed method under severe asymmetrical faults and different nonlinear loads than an existing peak detection (PD)-based CLS. Furthermore, state space analysis indicates the stability of the proposed control structure with different values for the reference current reduction coefficient specifying the fault depth indirectly.