An Optimization Algorithm for Dimensional Design of Graphene Nano-ribbon Field Effect Transistors for All-Graphene SRAM Chip

Abstract

This work presents a complete all-graphene SRAM chip design. The SRAM requires analog and digital sub-circuits, each having different design criteria. On the other hand, the electrical parameters of a GNRFET device are strongly related to geometry. In this study, we built a complete graphene-based SRAM chip and then proposed a new approach to optimize the GNRFET’s physical design which fulfills SRAM requirements for HOLD, READ, and WRITE operations. The effect of geometric and process parameters such as chirality, channel length, and width are investigated on the characteristics of an SRAM cell based on GNRFET. Analysis of power consumption, delay, and SNM results, indicate that adjustable parameters of GNRFETs can have significant effects on SRAM cell performance, and our approach is very effective in parameter optimization. Using optimized GNRFETs, a full-circuit SRAM chip is designed and analyzed. The noise margin test of the SRAM cell shows 188mV HSNM, and 240mV WSNM, while standby and leakage currents were 5, and 20 times smaller.