Thesis

Design and Simulation of Low Power Latch Circuit with Soft Error Tolerance

Design of  voltage to time converter suitable for time to digital converters

Optimizing Fractals Key Generation Using DSP48 Blocks on FPGA Architecture

Design of storage element suitable for time-to-digital converters

Design of Soft Error Resilient Sequential Elements in Digital Circuits

Digital Error Correction for Pipeline Analog to Digital Converter

Design and Optimization of Sampling Circuit in Low-Voltage Data Conversion Systems

Design & Optimization of APS Cell in Low Power, Low Voltage Image Sensors

Design and Optimization of Graphene based Scannable D-Flip-Flop

Design of Vernier Time  to Digital Converter With Tunable Resolution

Implementation & Optimization of CORDIC Algorithm Using DSP48 Hardware Multiplier Block

Design and Optimization of All Digital Process Variation and Aging Measurement Sensor

Design and Simulation of Image Sensor Based on 2D Material and Comparison with the improved Geometry Detector

Design and Optimization of I/O Block Based on Graphene Nano-Ribbon FETs (GNRFETs)

Design of readout circuit for smart image sensor with the aim of hardware-level implementation of image processing filters